DEVELOPMENT OF MODEL AND STRUCTURE OF CONTROL DEVICES WITH PARALLEL ARCHITECTURE

Abstract

Topicality. Over the past decade, not much attention has been devoted to the development and improvement of information technology of parallel logic control based on parallel FPGA controllers. At the same time, recent studies have shown that the improvement of this technology, the introduction of new functionality into its composition, will allow to significantly expand the scope of its application not only for the control of objects of critical application, but also for the construction of control systems for ordinary industrial objects. objects One such improvement that greatly expands the functionality of parallel FPGA controllers is the introduction of internal timers and counters. The purpose of this work is to improve the mathematical model and architecture of the parallel action programmable logic controller and expand its functionality by introducing programmed timers into its composition. Conclusion. According to the results of the conducted research, the structure of an improved logical control automaton of parallel action was synthesized, in which the possibility of implementing programmable timers was added. The elements of the mathematical model of LKA PD have been improved, it has been shown how the introduction of additional internal variables affects the implementation of the main mathematical dependencies that determine its functioning. On the basis of the proposed structure and elements of the mathematical model, it becomes possible to build an improved functioning algorithm and an HDL model for the physical implementation of a FPGA controller of parallel action.