FEATURES OF HARDWARE IMPLEMENTATION OF THE MULTIPLIER BASED ON THE MODIFIED WALLACE TREE
Keywords:
digital signal processor, hardware multiplier, Wallace tree, Field-Programmable Gate ArrayAbstract
Features of the hardware implementation of the multiplier, which uses the structure of the Wallace tree. Еstimated the hardware cost for the implementation of this multiplier using Altera’s FPGA Stratix IV. Compared performance characteristics with embedded multiplication block which is provided by vendor on license agreement.
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References
Орлов, С.А. Организация ЭВМ и систем : учебник для вузов / С.А. Орлов, Б.Я. Цилькер. - СПб.: Питер, 2011. - 688 с.
Кормен, Т., Лейзерсон, Ч., Ривест, Р. Алгоритмы: построение и анализ. — 960 с.
Солонина А.И., Улахович Д.А., Яковлев Л.А. Алгоритмы и процессоры цифровой обработки сигналов. – СПб: БХВ-Петербург, 2001. — 464 с.
Earle, J. G. et al U.S. Patent 3 340 388 «Latched Carry Save Adder Circuit for Multipliers» filed July 12, 1965.
Joel Hatsch, Winfried Kamp, Siegmar Koppe, Ronald Kunemund, Eva Lackerschmid, Heinz Soldner U.S. Patent U.S. 20 040 159 712 «6-To-3 bit carry-save adder» filed Augest 19, 2004.
Avinash M. Ghorpade, Amey Mahadeo Muchandi «Multiplier Design Using Carry Save Adder», IJAREEIE. Vol. 5, Issue 4, April 2016.
Jasbir Kaur and Kavita, “Structural VHDL Implementation of Wallace Multiplier”, International Journal of Scientific & Engineering Research, vol. 4, Issue. 4, pp. 1829-1833, April 2013.
