ADVANCED PACKAGING TECHNOLOGIES FOR INTEGRATED CIRCUITS

Abstract

Relevance. Given the global surge in demand for advanced semiconductor solutions, improving advanced packaging technologies is strategically important for the electronics industry. The purpose of this work is to analyze current trends and major challenges associated with advanced IC packaging technologies to support the selection of optimal chiplet interconnect testing models. The object of study is IC layout and packaging technologies. The subject of study includes technological solutions and design features of advanced IC packaging and layout. These include 2,5D integration, which enables ultra-high interconnect density, such as silicon interposer-based integration (CoWoS) and embedded multi-die interconnect bridge (EMIB). The study also considers materials and related technological processes that contribute to the creation of effective interconnects. Results. The study analyzes the key issues that accompany modern packaging technologies, including parasitic electrical characteristics, thermal loads, and mechanical stress, all of which can affect IC longevity and performance. It examines the advantages and drawbacks of advance packaging methods, particularly 2,5D integration technologies, which significantly improve component integration density, reduce electrical interconnect lengths, and enhance heat dissipation. A basic implementation of CoWoS and EMIB structures in Verilog hardware description language is presented as a starting point for building more complex simulation models.