ІNCREASING THE ACCURACY OF FUNCTIONING OF PHASE-LOCKED LOOP ACCORDING TO THE INDICATIVE CHARACTERISTICS OF SIGNALS

Abstract

From the analysis of recent research and publications by the authors, it is found that all practical implementations of phase-locked frequency synthesizers (PLLs) suffer from unwanted frequency components, and since these components significantly affect the performance of the system, the task of their prediction and minimization arises. The article considers the principles of operation of the reference frequency divider Q, the divider in the feedback loop P and the output frequency divider N on the PLL, their influence on the system operation. A block diagram of a PLL with one output frequency is presented. The pseudocode of the algorithm for finding the most optimal system characteristics is demonstrated. The work of the algorithm is illustrated on the example of synthesizing the output frequency of 50 MHz based on the reference signal, which uses the usual frequency of the video signal. The main parameters of the system are considered in detail, namely consumption, startup and settling frequency, jitter, phase noise, and the relationships between their limits are considered. It was determined that the consumption is determined by the frequency of the voltage-controlled oscillator (VCO), the charge pumping current and the parameters of the frequency dividers. In most VCOs, high currents are required to achieve higher frequencies, which means that power consumption increases with increasing frequency. The startup and settling time for a PLL is determined by the natural frequency of the loop, this parameter is considered an indicator of the rate of change of the PLL frequency. It was established that in order to minimize the time of startup and settling, it is necessary to increase the gain factor of the VCO and the pumping current, and the separation factor in the feedback circuit and the capacity of the filter, on the contrary, should be set to the minimum value. It is also determined in the work that the lower the gain factor of the VCO, the less sensitive the PLL circuit is to the drift of the filter voltage. The authors found that it is convenient to use the original division factor of the divider N to reduce phase noise. It was established that when using a low-noise output divider, the phase noise can be reduced by increasing the frequency of operation of the VCO and increasing the division coefficient of the output frequency N. Examples of the use of configurations are given.