THE AUTOMATON MODELS AND SYNTHESIS OF MONITORING MEANS FOR HARDWARE IMPLEMENTATION OF CACHE MEMORY SUBSTITUTION ALGORITHMS

Abstract

The synthesis of automatic models of pseudo algorithm substitution policies - LRU, adaptive ARC and MRU shows that the output combinational selection logic of selecting elements of the cache data unit in q directions is an indispensable component of the model. This component is taken from the logical equations of structure synthesis, which describe the logical operation of the decoder. It is known that a typical combinational logic of the decoder turns a binary code into a unitary code and this is a condition of its error-free operation. Thus, the conditions of erroneous operation will be output binary combinations that differ from the combinations of a unitary code. Two options of the synthesis for monitoring means of the decoder operation logic is implemented in the paper. The first option is based on the automaton model of hardware monitoring with memory elements with next synthesis for obtaining the minimum normal recording form of the switching function, which describing the logic of the operation for the combinational scheme of the “and-not” basis. The second option is based on the idea of counting of logical units at the outputs of the combination logic selection in q - directions. Such memory elements as a synchronous shift registers and a synchronous binary counter with additional logic for controlling the input of a counter increment were included in the structure of the automatic model for this. The comparison component with constant value of logical unit is a binary comparator with the output result of a comparison function for definition of the existence or the absence of error. In addition, the article gives the calculation of such parameters of the technical diagnostics as the reliability of control, the reliability of functioning, the increase in the reliability of functioning and efficiency of control and diagnostic efficiency factor